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1 low voltage, single and dual supply, 8-to-1 multiplexer, dual 4-to-1 multiplexer and a triple spdt analog switch isl84051, isl84052, isl84053 the intersil isl84051, isl84052, isl84053 devices are precision, bidirectional, anal og switches configured as a 8-channel multiplexer/demultiplexer (isl84051), a dual differential 4-channel multiplexer/demultiplexer (isl84052) and a triple single pole/double throw (spdt) switch (isl84053) designed to operate from a single +2v to +12v supply or from a 2v to 6v supply. all devices have an inhibit pin to simultaneously open all signal paths. on-resistance is 60 ? with a 5v supply and 125 ? with a single +5v supply. each switch can handle rail to rail analog signals. the off-leakage current is only 5na at +85c with a 5v supply. all digital inputs have 0.8v to 2.4v logic thresholds, ensuring ttl/cmos logic compatibility when using a single +3.3v and +5v supply or dual 5v supplies. the isl84051 is a 8-to-1 multiplexer device. the isl84052 is a dual 4-to-1 multiplexer device . the isl84053 is a committed triple spdt, which is perfect for use in 2-to-1 multiplexer applications. table 1 summarizes the performance of this family. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? features ? drop-in replacements for max4051/max4051a, max4052/max4052a and max4053/max4053a ? pin compatible with max4 581, max4582, max4583 and with industry standard 74hc4051, 74hc4052 and 74hc4053 ? on-resistance (r on ) max, v s = 5v . . . . . . . . . . . . . . . . . 100 ? ? on-resistance (r on ) max, v s = +5v . . . . . . . . . . . . . . . . . 225 ? ?r on matching between channels . . . . . . . . . . . . . . . . . . . . . . <6 ? ? low charge injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2pc ? single supply operation. . . . . . . . . . . . . . . . . . . . . . . +2v to +12v ? dual supply operation . . . . . . . . . . . . . . . . . . . . . . . . . . 2v to 6 ? fast switching action (v s = +5v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns ? guaranteed max off-leakage @ v s = 5v . . . . . . . . . . . . . . 5na ? break-before-make ? ttl, cmos compatible ? pb-free available (rohs compliant) applications ? portable equipment ? communications systems -radios - telecom infrastructure -adsl, vdsl modems ?test equipment - medical ultrasound - magnetic resonance image - ct and pet scanners (mri) -ate - electrocardiograph ? audio and video signal routing ? various circuits - +3v/+5v dacs and adcs - sample and hold circuits - operational amplifier gain switching networks - high frequency analog switching - high speed multiplexing - integrator reset circuits table 1. features at a glance configuration isl84051 isl84052 isl84053 8:1 mux dual 4:1 mux triple spdt 5v r on 60 ? 60 ? 60 ? 5v t on /t off 50ns/40ns 50ns/40ns 50ns/40ns 5v r on 125 ? 125 ? 125 ? 5v t on /t off 90ns/60ns 90ns/60ns 90ns/60ns 3v r on 250 ? 250 ? 250 ? 3v t on /t off 180ns/100ns 180ns/100ns 180ns/100ns packages 16 ld soic 16 ld soic 16 ld soic 16 ld qsop 16 ld qsop 16 ld qsop 16 ld tssop 16 ld tssop 16 ld tssop may 16, 2011 fn6047.10 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2003, 2004, 2006, 2007, 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl84051, isl84052, isl84053 2 fn6047.10 may 16, 2011 pin configurations isl84051 (16 ld soic, qsop, tssop) top view isl84052 (16 ld soic, qsop, tssop) top view isl84053 (16 ld soic, qsop, tssop) top view note: 1. switches shown for logic ?0? inputs. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 no1 no3 com no7 no5 inh gnd v- v+ no4 no0 no6 addc addb adda no2 logic 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 no0b no1b comb no3b no2b inh gnd v- v+ no2a coma no0a no3a addb adda no1a logic 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 nob ncb noa coma nca inh gnd v- v+ comc noc ncc addc addb adda comb pin description pin name pin number function isl84051 isl84052 isl84053 v+ 16 16 16 positive power supply input v- 7 7 7 negative power supply input. connect to gnd for single supply configurations. gnd 8 8 8 ground connection inh 6 6 6 digital control input. connect to gnd for normal operation. connect to v+ to turn all switches off. com 3 - - analog switch common pin coma - 13 4 comb - 3 15 comc - - 14 no1, no3, no7, no5, no6, no4, no2 1, 2, 4, 5, 12, 14, 15 - - analog switch normally open pin
isl84051, isl84052, isl84053 3 fn6047.10 may 16, 2011 no0b, no1b, no3b, no2b, no3a, no0a, no2a, no1a -1, 2, 4, 5, 11, 12, 14, 15 - analog switch normally open pin nob, noa, noc - - 1, 3, 13 ncb, nca, ncc - - 2, 5, 12 analog switch normally closed pin adda, addb, addc 9, 10 11 9, 10 - 9, 10 11 address input pin pin description (continued) pin name pin number function isl84051 isl84052 isl84053 ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl84051iaz 84051 iaz -40 to +85 16 ld qsop m16.15a isl84051ibz 84051ibz -40 to +85 16 ld soic m16.15 isl84051ivz 84051 ivz -40 to +85 16 ld tssop m16.173 isl84052iaz 84052 iaz -40 to +85 16 ld qsop m16.15a isl84052ibz 84052ibz -40 to +85 16 ld soic m16.15 isl84052ivz 84052 ivz -40 to +85 16 ld tssop m16.173 isl84053iaz 84053 iaz -40 to +85 16 ld qsop m16.15a isl84053ibz 84053ibz -40 to +85 16 ld soic m16.15 isl84053ivz 84053 ivz -40 to +85 16 ld tssop m16.173 notes: 2. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020 4. for moisture sensitivity level (msl), please see device information page for isl84051, isl84052, isl84053 . for more information on msl please see techbrief tb363 .
isl84051, isl84052, isl84053 4 fn6047.10 may 16, 2011 truth tables isl84051 inh addc addb adda switch on 1xxxnone 0000no0 0001no1 0010no2 0011no3 0100no4 0101no5 0110no6 0111no7 isl84052 inh addb adda switch on 1xxnone 000no0 001no1 010no2 011no3 isl84053 inh add c add b add a switch on 1 x xxnone 0xx0nc a 0xx1no a 0x0xnc b 0x1xno b 00xxnc c 01xxno c note: logic ?0? 0.8v. logic ?1? 2.4v, with v+ between 2.7v and 10v. x = don?t care.
isl84051, isl84052, isl84053 5 fn6047.10 may 16, 2011 absolute maximum rating s thermal information v+ to v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v v- to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15v to 0.3v input voltages inh, no, nc, add (note 5). . . . . . . . . . . . . . . . ((v-) - 0.3) to ((v+) + 0.3v) output voltages com (note 5). . . . . . . . . . . . . . . . . . . . . . . . . . . ((v-) - 0.3) to ((v+) + 0.3v) continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . 30ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max). . . . . . . . . . . . . . . . . . . . . . . . 100ma esd rating human body model (per mil-std-883, method 3015.7) . . . . . . . . >2kv thermal resistance (typical, notes 6, 7) ja (c/w) jc (c/w) 16 ld soic package . . . . . . . . . . . . . . . . . . 75 39 16 ld qsop package. . . . . . . . . . . . . . . . . . 95 56 16 ld tssop package . . . . . . . . . . . . . . . . . 110 33 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. signals on nc, no, com, add, or inh exceeding v+ or v- are cl amped by internal diodes. limit forward diode current to maximum current ratings. 6. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 7. for jc , the ?case temp? location is taken at the package top center. electrical specifications 5v supply test conditions: v supply = 4.5v to 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full v- - v+ v on-resistance, r on v s = 5v, i com = 1ma, v no or v nc = 3v (see figure 5) +25 - 60 100 ? full - - 125 ? r on matching between channels, r on v s = 5v, i com = 1ma, v no or v nc = 3v (note 11) +25 - - 6 ? full - - 12 ? r on flatness, r flat(on) v s = 5v, i com = 1ma, v no or v nc = 3v, 0v (note 12) +25 - - 10 ? full - - 15 ? no or nc off leakage current, i no(off) or i nc(off) v s = 5.5v, v com = 4.5v, v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -5 - 5 na com off leakage current, i com(off) , (isl84051) v s = 5.5v, v com = 4.5v, v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -5 - 5 na com off leakage current, i com(off) , (isl84052, isl84053) v s = 5.5v, v com = 4.5v, v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -2.5 - 2.5 na com on leakage current, i com(on) , (isl84051) v s = 5.5v, v com = v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -5 - 5 na com on leakage current, i com(on) , (isl84052, isl84053) v s = 5.5v, v com = v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -2.5 - 2.5 na digital input characteristics input voltage high, v inh , v addh full 2.4 --v input voltage low, v inl , v addl full - - 0.8 v input current, i inh , i inl , i addh , i addl v s = 5.5v, v inh , v add = 0v or v+ full -1 0.03 1 a
isl84051, isl84052, isl84053 6 fn6047.10 may 16, 2011 dynamic characteristics inhibit turn-on time, t on v s = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 50 - ns full - 60 - ns inhibit turn-off time, t off v s = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 40 - ns full - 50 - ns address transition time, t trans v s = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 75 - ns break-before-make time, t bbm v s = 5.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 3) +25 - 10 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? (see figure 2) +25 - 2 - pc no/nc off-capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) +25 - 3 - pf com off-capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) isl84051 +25 - 21 - pf isl84052 +25 - 12 - pf isl84053 +25 - 9 - pf com on-capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) isl84051 +25 - 26 - pf isl84052 +25 - 18 - pf isl84053 +25 - 14 - pf off isolation r l = 50 ? , c l = 15pf, f = 100khz v no or v nc = 1v rms (see figures 4 and 6) +25 - <90 - db crosstalk, (note 9) (isl84052, isl84053 only) +25 - < -90 - db power supply characteristics power supply range full 2 - 6 v positive supply current, i+ v s = 5.5v, v inh , v add = 0v or v+, switch on or off +25 -1 0.1 1 a full -10 - 10 a negative supply current, i- 25 -1 0.1 1 a full -10 - 10 a electrical specifications 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 5v, i com = 1.0ma, v no or v nc = 3.5v (see figure 5) +25 - 125 225 ? full - - 280 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 0v, 4.5v, v no or v nc = 4.5v, 0v (note 12) +25 - 0.002 - na full -10 - 10 na com off leakage current, i com(off) , (isl84051) v+ = 5.5v, v com = 0v, 4.5v, v no or v nc = 4.5v, 0v (note 12) +25 - 0.002 - na full -10 - 10 na com off leakage current, i com(off) , (isl84052, isl84053) v+ = 5.5v, v com = 0v, 4.5v, v no or v nc = 4.5v, 0v (note 12) +25 - 0.002 - na full -5 - 5 na electrical specifications 5v supply test conditions: v supply = 4.5v to 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating te mperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units
isl84051, isl84052, isl84053 7 fn6047.10 may 16, 2011 com on leakage current, i com(on) v+ = 5.5v, v com = v no or v nc = 4.5v (note 12) +25 - 0.002 - na full -10 - 10 na digital input characteristics input voltage high, v inh , v addh full 2.4 --v input voltage low, v inl , v addl full - - 0.8 v input current, i inh , i inl , i addh , i addl v+ = 5.5v, v inh , v add = 0v or v+ full -1 0.03 1 a dynamic characteristics inhibit turn-on time, t on v+ = 4.5v, v no or v nc = 3v, r l = 300 ? , c l =35pf, v in = 0 to 3v (see figure 1) +25 - 90 - ns full - 100 - ns inhibit turn-off time, t off v+ = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 60 - ns full - 70 - ns break-before-make time, t bbm v+ = 5.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 3) +25 - 30 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? (see figure 2) +25 - 2 - pc off isolation r l = 50 ? , c l = 15pf, f = 100khz v no or v nc =1v rms (see figures 4 and 6) +25 - <90 - db crosstalk, (note 9) (isl84052, isl840533 only) +25 - <-90 - db power supply characteristics power supply range full 2 - 12 v positive supply current, i+ v+ = 5.5v, v- = 0v, v inh , v add = 0v or v+, switch on or off +25 -1 - 1 a full -10 - 10 a electrical specifications 3.3v supply test conditions: v+ = +3.0v to +3.6v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 3v, i com = 1.0ma, v no or v nc = 1.5v +25 - 250 - ? full - 270 - ? no or nc off leakage current, i no(off) or i nc(off) v+ = 3.6v, v com = 0v, 3v, v no or v nc = 3v, 0v (note 12) +25 - 0.002 - na full -10 - 10 na com off leakage current, i com(off) , (isl84051) v+ = 3.6v, v com = 0v, 3v, v no or v nc = 3v, 0v (note 12) +25 - 0.002 - na full -10 - 10 na com off leakage current, i com(off) , (isl84052, isl84053) v+ = 3.6v, v com = 0v, 3v, v no or v nc = 3v, 0v (note 12) +25 - 0.002 - na full -5 - 5 na com on leakage current, i com(on) v+ = 3.6v, v com = v no or v nc = 3v (note 12) +25 - 0.002 - na full -10 - 10 na digital input characteristics input voltage high, v inh , v addh full 2.4 --v electrical specifications 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units
isl84051, isl84052, isl84053 8 fn6047.10 may 16, 2011 input voltage low, v inl , v addl full - - 0.8 v input current, i inh , i inl , i addh , i addl v+ = 3.6v, v inh , v add = 0v or v+ full -1 0.03 1 a dynamic characteristics inhibit turn-on time, t on v+ = 3v, v no or v nc = 1.5v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 180 - ns full - 280 - ns inhibit turn-off time, t off v+ = 3v, v no or v nc = 1.5v, r l = 300 ? , c l = 35pf, v in = 0v to 3v (see figure 1) +25 - 100 - ns full - 200 - ns break-before-make time, t bbm v+ = 3.6v, v no or v nc = 1.5v, r l = 300 ? , c l =35pf, v in = 0v to 3v (see figure 3) +25 - 90 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? (see figure 2) +25 - 1 - pc off isolation r l = 50 ? , c l = 15pf, f = 100khz v no or v nc = 1v rms , (see figures 4 and 6) +25 - <90 - db crosstalk, (note 9) (isl84052, isl84053 only) +25 - <-90 - db power supply characteristics power supply range full 2 - 12 v positive supply current, i+ v+ = 3.6v, v- = 0v, v inh , v add = 0v or v+ switch on or off +25 -1 - 1 a full -10 - 10 a notes: 8. v in = input voltage to perform proper function. 9. the algebraic convention, whereby the most negative value is a mi nimum and the most positive a ma ximum, is used in this data sheet. 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. r on = r on (max) - r on (min). 12. flatness is defined as the difference between maximum and mini mum value of on-resistance over the specified analog signal ra nge. 13. between any two switches. electrical specifications 3.3v supply test conditions: v+ = +3.0v to +3.6v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 8), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 9, 10) typ max (notes 9, 10) units
isl84051, isl84052, isl84053 9 fn6047.10 may 16, 2011 test circuits and waveforms figure 1a. inhibit t on /t off measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1b. inhibit t on /t off test circuit figure 1. switching times 50% t r < 20ns t f < 20ns t on 3v 0v t off logic input switch output 90% 0v 90% v out logic input waveform is inverted for switches that have the opposit e logic sense. v out v (no or nc) r l r l r on + ---------------------- = logic input v out r l com no0 inh 300 ? 35pf gnd v- c no1-no7 c l v+ adda-c c logic input v out r l com x nc x inh 300 ? 35pf gnd no x c l v+ add x c isl84051 isl84053 v+ c v- c v+ c logic input v out r l com no0 inh 300 ? 35pf gnd v- c no1-no3 c l v+ adda-b c isl84052 v+ c
isl84051, isl84052, isl84053 10 fn6047.10 may 16, 2011 figure 1c. address t trans measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1d. address t trans test circuit figure 1. switching times (continued) test circuits and waveforms (continued) 50% t r < 20ns t f < 20ns t trans 90% 3v vnox 0v t trans logic input switch output 10% v out 0v vnox logic input waveform is inverted for switches that have the opposit e logic sense. v out v (no or nc) r l r l r on + ---------------------- = logic input v out r l com no0 adda-c 300 ? 35pf gnd no1-no6 c l v+ inh c logic input v out r l com x nc x add x 300 ? 35pf gnd no x c l v+ inh c isl84051 isl84053 v- c v+ c v- c v+ c no7 v- c logic input v out r l com no0 adda-b 300 ? 35pf gnd no1-no2 c l v+ inh c isl84052 v- c v+ c no3 v- c v- c
isl84051, isl84052, isl84053 11 fn6047.10 may 16, 2011 figure 2a. q measurement points figure 2b. q test circuit figure 2. charge injection figure 3a. t bbm measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 3b. t bbm test circuit figure 3. break-before-make time test circuits and waveforms (continued) v out dv out off on off q = dv out x c l switch output logic input 3v 0v c l v out r g v g gnd com no or nc logic input inh addx v- c v+ c repeat test for other switches. 1nf 0 ? 80% 3v 0v t bbm logic input switch output 0v v out t r < 20ns t f < 20ns logic input adda-c com r l c l v out 35pf 300 ? no0-no7 gnd v+ c inh logic input add x com x r l c l v out 35pf 300 ? no x nc x gnd v+ inh c isl84051 isl84053 v- c v+ c v- c v+ c logic input adda-b com r l c l v out 35pf 300 ? no0-no3 gnd v+ c inh isl84052 v- c v+ c
isl84051, isl84052, isl84053 12 fn6047.10 may 16, 2011 detailed description the isl84051, isl84052, isl84053 analog switches offer precise switching capability from a bipolar 2v to 6v or a single 2v to 12v supply with low on-resistance (60 ? ) and high speed operation (t on =50ns, t off = 40ns). the devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2v), low power consumption (3w), low leakage currents (5na max). high frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to v- (see figure 8). to prevent forward biasing these diodes, v+ and v- must be applied before any input signal s, and input signal voltages must remain between v+ and v-. if these conditions cannot be guaranteed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k ? resistor in series with the input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not applicable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be figure 4. off isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator 0v or v+ no or nc com addx gnd inh 0v or v+ v- c v+ c 0v or v+ no or nc com addx gnd v nx v 1 r on = v 1 /1ma 1ma inh v- c v+ c 0v or v+ analyzer no a or nc a signal generator r l gnd addx 50 ? nc com b no b or nc b inh isl84052 v- c v+ c com a isl84053 and gnd no or nc com addx impedance analyzer 0v or v+ inh v- c v+ c
isl84051, isl84052, isl84053 13 fn6047.10 may 16, 2011 added in series with the supply pins to provide overvoltage protection for all pins (see figu re 8). these additional diodes limit the analog signal from 1v below v+ to 1v above v-. the low leakage current performanc e is unaffected by this approach, but the switch resist ance may increase, especially at low supply voltages. power-supply considerations the isl8405x construction is ty pical of most cmos analog switches, in that they have three supply pins: v+, v-, and gnd. v+ and v- drive the internal cmos switches and set their analog voltage limits, so there are no connections between the analog signal path and gnd. unlike switches with a 13v maximum supply voltage, the isl8405x 15v maximum supply voltage provides plenty of room for the 10% tolerance of 12v supplies (6v or 12v single supply), as well as room for overshoot and noise spikes. this family of switches performs equally well when operated with bipolar or single voltage supplies. the minimum recommended supply voltage is 2v or 2v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specification? tables beginning on page 5 and ?typical performance curves ? beginning on page 14 for details. v+ and gnd power the internal logic (thus setting the digital switching point) and level shifters. the level shifters convert the logic levels to switched v+ and v- signals to drive the analog switch gate terminals. logic-level thresholds v+ and gnd power the internal logic stages, so v- has no affect on logic thresholds. this switch family is ttl compatible (0.8v and 2.4v) over a v+ supply range of 2.7v to 10v. at 12v the v ih level is about 3.5v. this is still below the cmos guaranteed high output minimum level of 4v, but noise margin is reduced. for best results with a 12v su pply, use a logic family that provides a v oh greater than 4v. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 ? systems, signal response is reasonably flat even past 100mhz (see figure 17). figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch?s input to its output. off isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. figure 18 details the high off isolation and crosstalk rejection provided by this family. at 10mhz, off isolation is about 55db in 50 ? systems, decreasing approxim ately 20db per decade as frequency increases. higher load impedances decrease off isolation and crosstalk rejectio n due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and v-. one of these diodes conducts if any an alog signal exceeds v+ or v-. virtually all the analog leakag e current comes from the esd diodes to v+ or v-. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means th eir leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins constitutes the analog-signal-path leakage current. all analog leakage cu rrent flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of the same or opposite polarity. there is no connection between the analog signal paths and gnd. figure 8. input overvoltage protection v- v com v no or nc optional protection v+ logic diode optional protection diode optional protection resistor for logic inputs 1k ?
isl84051, isl84052, isl84053 14 fn6047.10 may 16, 2011 typical performance curves t a = +25c, unless otherwise specified figure 9. on-resistance vs supply voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage figure 12. charge injection vs switch voltage figure 13. inhibit turn-on time vs supply voltage figure 14. inhibit turn-off time vs supply voltage 30 40 50 60 70 100 200 300 400 -40c +85c v- = 0v r on ( ? ) v+ (v) 4681012 357911 2 0 20 v com = (v+) - 1v i com = 1ma v- = -5v +25c -40c +85c +25c 75 100 150 200 225 60 80 100 120 140 160 40 50 60 70 80 90 100 r on ( ? ) v com (v) 024 135 v+ = 2.7v v+ = 5v +25c -40c +85c i com = 1ma v- = 0v +25c -40c +85c v- = 0v +25c +85c -40c v- = 0v v+ = 3.3v 175 125 20 30 40 50 60 30 40 50 60 70 80 90 50 60 70 80 90 100 110 120 r on ( ? ) v com (v) -4 -2 0 2 4 -5 -3 -1 1 3 5 v s = 5v i com = 1ma v s = 2v +25c +85c +25c -40c +85c -40c +25c -40c +85c v s = 3v -3 -2 -1 0 1 2 q (pc) v com (v) -5 0 5 -2.5 2.5 v s = 5v v+ = 5v v- = 0v 0 100 200 300 400 500 0 50 100 150 200 250 t on (ns) v+ (v) 24681012 357911 -40c +85c v- = 0v v- = -5v v com = (v+) - 1v -40c +85c -40c +25c +25c +25c 0 50 100 150 200 0 20 40 60 80 100 t off (ns) v+ (v) 2 4 6 8 10 12 357911 -40c +85c v com = (v+) - 1v v- = 0v v- = -5v -40c +85c -40c +25c +25c +25c +85c
isl84051, isl84052, isl84053 15 fn6047.10 may 16, 2011 die characteristics substrate potential (powered up): v- transistor count: isl84051: 193 isl84052: 193 isl84053: 193 process: si gate cmos figure 15. address trans time vs single supply voltage figure 16. address trans time vs dual supply voltage figure 17. frequency response figure 18. crosstalk and off isolation typical performance curves t a = +25c, unless otherwise specified (continued) 24681012 35791113 v+ (v) +85c v- = 0v v com = (v+) - 1v -40c 0 50 100 150 200 250 300 t rans (ns) +25c v (v) 23456 v com = (v+) - 1v t rans (ns) 50 100 150 200 250 +85c -40c +25c 0 frequency (hz) 3 0 -3 normalized gain (db) 0 45 90 135 180 phase () 1m 10m 100m 600m v in = 0.2v p-p to 5v p-p gain phase v s = 5v r l = 50 ? isl84053 isl84051 isl84051 isl84053 isl84052 isl84052 frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation crosstalk r l = 50 ? v s = 2v to 5v v+ = 3v to 12v or
isl84051, isl84052, isl84053 16 fn6047.10 may 16, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl84051 , isl84052 , isl84053 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 05/02/11 fn6047.10 -converted to new datasheet template. -updated intersil trademark statement at bottom of page 1 per directive from legal. -added tssop package option to isl84053 in pin configuration and ordering information. -updated ordering information by removing with drawn and obsolete non pb-free parts: isl84051ia, isl84051ia-t, isl84051ib, isl84051ib-t, isl84052ia, isl84051ib, isl84053ia-t updated notes in ordering information -updated ?parameters...? note in electrical specificat ions tables to new ?compliance...? note according to standards -m16.173 - converted to new pod format by moving dimensions from table onto drawing and adding land pattern. no dimension changes. -added revision history and products information.
isl84051, isl84052, isl84053 17 fn6047.10 may 16, 2011 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 8 0 8 - rev. 1 6/05
isl84051, isl84052, isl84053 18 fn6047.10 may 16, 2011 package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
isl84051, isl84052, isl84053 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6047.10 may 16, 2011 for additional products, see www.intersil.com/product_tree shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 8 0 8 - rev. 2 6/04

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